CODE NAME ATHENA.
Athena, most intelligent and wisest of the gods.
CREATING A NEW MICROPROCESSOR CHAMPION FOR THE AGE OF UBIQUITOUS AI.
HYPERION Core drives a paradigm change: Software Defined Innovation. The differentiation of functionality for products is not defined by hardware but by software. It allows for flexibility in the development process and super-charged innovation. The Digital Economy is rapidly expanding. Artificial intelligence (AI) will be a main driver and will create up to $5.8 trillion in value annually (28% of US GDP). The foundation of the digital economy are microprocessors. Today’s microprocessors are not suitable for the Age of Ubiquitous AI. HYPERION Core’s novel processors are workload agnostic, hyper-flexible, high-performant and cost-effective.
TODAY’S MICROPROCESSORS ARE INFLEXIBLE.
WORKLOAD OPTIMIZED
CPU / GPU
Single purpose processing
SPECIFIC PURPOSE BUILT
SoC / ASIC / FPGA
Narrow purpose application
PROPRIETARY
Proprietary legacy ISA
Proprietary software stack
To meet usecase and application specific requirements, often tailored ASIC or SoC are deployed. Developmnet efforts are extremely high, changed are expensive, both in time and cost.
… UNIVERSAL PROCESSOR.
A workload agnostic universal processor would be hyper-flexible and significantly more cost-effective due to higher utilization.
A universal processor would allow efficient and cost effective processing.
… DISRUPTIVE PARADIGM CHANGE.
When it comes to product innovation – development, testing and potential changes to hardware design are costly and time consuming. The most value add is created with software that defines the user experience.
Software-defined innovations allow developing and launching products that fulfill not only today’s requirements but also tomorrow’s unknown market demand.
AN OPEN,UNIVERSAL PROCESSOR.
OPEN / NON-PROPRIETARY
WORKLOAD AGNOSTIC & HYPER-FLEXIBLE
LOW COST & LOW POWER CONSUMPTION
SCALABLE PROCESSING POWER / MICRO-ARCHITECTURE
NOVEL MICRO-ARCHITECTURE BACKED BY
13 PATENTS &
5 APPLICATIONS.
ARRAY OF PROCESSING ELEMENTS
INSTRUCTION LEVEL PARALLELISM
OPEN STANDARD RISC-V ISA
HYPERION Core is based on a RISC-V in-order front end, containing branch prediction and branch target buffers. Up to 8 instructions are in parallel and in-order decoded and issued from the Instruction Cache to the Array of Processing Elements.
The Array operates in two modes: Out-of-Order and Loop Acceleration.
HYPERION CORE ARCHITECTURE SUPPORTS DIFFERENT OPERATION MODES.
OUT-OF-ORDER
Issued instructions are stored in the respective Processing Elements (PE) until the required operands arrive. Then the instruction is executed out-of-order, only driven by operand availability, and the result stored in the Processing Element’s result register. Produced results are transferred through an efficient network to other PEs as operand data.
A plurality of threads can compete for array resources, allowing for efficient Hyperthreading.
The Array combines the conventional Reservation Station, Register File/Reorder Buffer and Execution Unit in a single regular arrangement, optimizing silicon efficiency. A small 256 PE Array provides an instruction window of approx. 225 instructions, which is about the same size of an Intel i7 processor.
LOOP ACCELERATION
Instructions are configured into PEs and a fixed data-path is set up as required by the register dependencies of the assembly code. The once configured instructions and data-path remain static until the respective algorithm (loop) terminates. No further instruction issue is required. Data is streamed and pipelined through the configured data-path providing highest Instruction Level Parallelism at lowest power dissipation. This mode is very similar to an FPGA.
In this mode the L2 cache operates as Tightly Coupled Memory (TCM) which is automatically loaded and offloaded from higher level (e.g. L3) memories. Each PE has a local window (indicated by the dark grey rectangle on the right hand side of each PE) into the L2 cache which enables local scratchpad memory or constant buffers (e.g. for AI parameters).
6x
FASTER PER
TRANSISTOR COUNT.
Frames / Second
600x
MORE ENERGY
EFFICIENT.
Images / Second per Watt
See Application Notes: BERT-6.0.pdf, ResNet50-0.31.pdf, YOLOv3-1.31.pdf, SVD5.1.pdf
A DISRUPTIVE MICROPROCESSOR FOR THE AGE OF UBIQUITOUS AI:
HYPER-FLEXIBLE, HIGH PERFORMANCE & LOW COST.
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