CODE NAME ATHENA.
Athena, most intelligent and wisest of the gods.
CREATING A NEW MICROPROCESSOR CHAMPION FOR THE AGE OF UBIQUITOUS AI.
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HYPERION Core drives a paradigm change: Software Defined Innovation. The differentiation of functionality for products is not defined by hardware but by software. It allows for flexibility in the development process and super-charged innovation. The Digital Economy is rapidly expanding. Artificial intelligence (AI) will be a main driver and will create up to $5.8 trillion in value annually (28% of US GDP). The foundation of the digital economy are microprocessors. Today’s microprocessors are not suitable for the Age of Ubiquitous AI. HYPERION Core’s novel processors are workload agnostic, hyper-flexible, high-performant and cost-effective.
FASTER, MORE EFFICIENT & HYPER-FLEXIBLE.
6x
FASTER PER
TRANSISTOR COUNT.
Frames / Second
600x
MORE ENERGY
EFFICIENT.
Images / Second per Watt
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See Application Notes: BERT-6.0.pdf, ResNet50-0.31.pdf, YOLOv3-1.31.pdf, SVD5.1.pdf.
Please contact HYPERION Core for more information.
TODAY’S MICROPROCESSORS ARE INFLEXIBLE.
WORKLOAD OPTIMIZED
CPU / GPU
Single purpose processing
SPECIFIC PURPOSE BUILT
SoC / ASIC / FPGA
Narrow purpose application
PROPRIETARY
Proprietary legacy ISA
Proprietary software stack
To meet usecase and application specific requirements, often tailored ASIC or SoC are deployed. Development efforts are extremely high, changes are expensive, both in time and cost.
… UNIVERSAL PROCESSOR.
A workload agnostic universal processor would be hyper-flexible and significantly more cost-effective due to higher utilization.
A universal processor would allow efficient and cost effective processing.
… DISRUPTIVE PARADIGM CHANGE.
When it comes to product innovation – development, testing and potential changes to hardware design are costly and time consuming. The most value add is created with software that defines the user experience.
Software-defined innovations allow developing and launching products that fulfill not only today’s requirements but also tomorrow’s unknown market demand.
AN OPEN,UNIVERSAL PROCESSOR BASED ON RISC-V.
OPEN / NON-PROPRIETARY
WORKLOAD AGNOSTIC & HYPER-FLEXIBLE
LOW COST & LOW POWER CONSUMPTION
SCALABLE PROCESSING POWER / MICRO-ARCHITECTURE
NOVEL MICRO-ARCHITECTURE BACKED BY
13 PATENTS &
5 APPLICATIONS.
ARRAY OF PROCESSING ELEMENTS
INSTRUCTION LEVEL PARALLELISM
OPEN STANDARD RISC-V ISA
HYPERION Core is based on a RISC-V in-order front end, containing branch prediction and branch target buffers. Up to 8 instructions are in parallel and in-order decoded and issued from the Instruction Cache to the Array of Processing Elements.
The Array operates in two modes: Out-of-Order and Loop Acceleration.
OUT-OF-ORDER
LOOP ACCELERATION
EXPERIENCED TEAM.
PETER W WEBER / CEO
Peter is a veteran of the high-tech industry. He started his career in Europe with Texas Instruments and Signetics followed by executive management positions with Intel in Europe and the US, Siliconix, the TEMIC Group and Netro Corporation.
Since 1998 Peter has been an investor and business angel and serves on the Boards of private and public companies in Europe and the US.
He met Martin while he was Chairman of PACT XPP Technologies AG.
MARTIN VORBACH / CTO
Martin started his first microprocessor company while still in highschool. He founded PACT XPP Technologies, a leader in the field of reconfigurable processors. PACT’s technology has been licensed to major US semiconductor companies.
Recognizing the limitations of today’s leading microprocessor architectures, he joined forces with Peter to found Hyperion-Core.
Martin has more than 200 patents in his name.
A DISRUPTIVE MICROPROCESSOR FOR THE AGE OF UBIQUITOUS AI:
HYPER-FLEXIBLE, HIGH PERFORMANCE & LOW COST.
WANT TO KNOW MORE? PLEASE GET IN TOUCH.
Email us at
info@hyperion-core.com
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